Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

stswp.h Rp[disp], Rs 

temp[15:0] = (Rs[7:0], Rs[15:8]);
*(Rp+SE(disp12) << 1) = temp[15:0];
 
{s, p} ∈ {0, 1, …, 15}
disp ∈ {-4096, -4094, ..., 4094}

Rev1+

111

Rp

11101

Rs

1001

disp12

3

4

5

4

4

12

2

stswp.wRp[disp], Rs 

temp[31:0] = (Rs[7:0], Rs[15:8], Rs[23:16], Rs[31:24]);
*(Rp+SE(disp12) << 2) = temp[31:0];
 
{s, p} ∈ {0, 1, …, 15}
disp ∈ {-8192, -8188 ..., 8188}

Rev1+

111

Rp

11101

Rs

1010

disp12

3

4

5

4

4

12

Description

This instruction swaps the bytes in a halfword or a word in the register file and stores the result to memory. The instruction can be used for performing stores to memories of different endianness.

Status Flags:

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

Not affected

C:

Not affected